1. Field of the Invention
The present invention relates to a semiconductor device capable of adjusting an output impedance of an output impedance adjustable output buffer of an external semiconductor device connectable to the semiconductor device, and an output impedance adjusting method.
2. Description of the Related Art
Semiconductor devices (chips) such as a double data rate 2 synchronous dynamic random access memory (DDR2 SDRAM) have no output impedance adjusting function therein. In such semiconductor devices, an off-chip driver impedance (OCD) adjusting function is incorporated thereinto, so that the output impedances of the semiconductor devices are adjusted by another semiconductor device (chip) such as a direct memory access (DMA) controller. Regarding the OCD impedance adjustment, refer to JEDEC Solid State Technology Association, “JEDEC Standard DDR2 SDRAM SPECIFICATION”, JESD79-2A, January 2004.
In a first prior art semiconductor apparatus where a semiconductor device such as a DMA controller including an output impedance adjustable output buffer adjusts the output impedance of an output impedance adjustable output buffer of an external semiconductor device such as a DDR2 SDRAM connected by a transmission line to the DMA controller, first, the output impedance of an output impedance adjustable output buffer of the DMA controller is adjusted. Then, one of the output impedance adjustable output buffers is controlled to generate a high level signal and the other is controlled to generate a low level signal, so that a current path is established from a power supply terminal through the two output impedance adjustable output buffers to a ground terminal. In this state, a comparator compares an input voltage, i.e., the output voltage of the output impedance adjustable output buffer of the DMA controller with a definite reference voltage such as VDD/2 where VDD is the power supply voltage. An output impedance control circuit transmits an output signal of the comparator to the DDR2 SDRAM to adjust the output impedance of the output impedance adjustable output buffer of the DDR2 SDRAM, so that the input voltage is made equal to VDD/2. This will be explained later in detail.
In a second prior art semiconductor apparatus where a semiconductor device such as a DMA controller including two output impedance adjustable differential output buffers adjusts the output impedances of two output impedance adjustable differential output buffers of an external semiconductor device such as a DDR2 SDRAM connected by transmission lines to the DMA controller, first, the output impedance adjustable differential output buffers of the DMA controller are controlled to be in a high impedance (Hz) state. Then, one of the output impedance adjustable differential output buffers of the DDR2 SDRAM is controlled to generate a high level signal and the other is controlled to generate a low level signal, so that a current path is established from a power supply terminal through the two output impedance adjustable differential output buffers via a turned-ON switch to a ground terminal. In this state, a comparator compares an input voltage, i.e., the center output voltage of the output impedance adjustable differential output buffers of the DDR2 SDRAM with a definite reference voltage such as VDD/2 where VDD is the power supply voltage. An output impedance control circuit transmits an output signal of the comparator to the DDR2 SDRAM to adjust the output impedance of the output impedance adjustable output buffer of the DDR2 SDRAM, so that the input voltage is made equal to VDD/2. This will be explained later in detail.